By increasing the number of levels of interconnects in integrated circuits provides additional routing capability, more compact layouts, better circuit performance and greater use of circuit design within a given integrated circuit surface area. A particularly useful level of connection is commonly called local interconnection, where neighboring diffused areas are connected to one another, and to neighboring polysilicon and metal lines.
For example, a conventional method for creating local interconnects uses metal interconnection of diffused regions to one another, as well as to other layers. The metal interconnection is formed by etching vias through a thick oxide layer to the locations to be interconnected. A conductor is then formed to fill the vias and make the connection. This method is limited, for purposes of reducing the area required for such connection, by the state of the technology of etching contact holes and the planarization of interlevel dielectrics. These limitations include the alignment tolerance of the vias to the underlying region to be connected, the size of the via required (and accordingly the size of the contact area in the underlying region) which can be reliably etched, and the step coverage of the conductor in filling the via and making good ohmic contact to the underlying region. Also, the additional layer of a metallic conductor across the dielectric contributes to a loss of planarization in subsequent levels.
An alternative method developed by Hewlett Packard and published at page 118 of the 1984 IEDM Proceedings uses additional patterned silicon to provide conductive silicide regions extending over the field oxide as desired. A layer of titanium is deposited over the substrate and, prior to the direct reaction of the titanium with the underlying silicon to form the silicide, a thin layer of silicon is patterned on top of the titanium metal to define an interconnect extending over a silicon dioxide region separating the two regions to be interconnected. Where this silicon layer remains, a silicide is formed during the reaction process extending over the oxides. This method requires the deposition and patterning of the additional layer of silicon to define the local interconnection. In addition, the resulting silicide strap provides a conduit through which typical n-type dopants such as phosphorous can diffuse, since titanium silicide is a very poor diffusion barrier to conventional semiconductor dopants. If a silicide strap is used to connect n-type regions to p-type regions, for example n-doped polysilicon to b-type diffusion, subsequent processing must be done at relatively low temperatures to minimize the counterdoping of the p-type region with the n-type dopant through the silicide interconnect.
Another known method uses molybdenum metal as a local interconnect material. Molybdenum, however, also acts as a diffusion conduit through which phosphorus, used to dope n-type regions of the semiconductor device, can diffuse. The molybdenum interconnect therefore is not an effective local interconnect between n-type and p-type regions, as the p-type regions can be undesirably counterdoped by the phosphorous diffusing through the molybdenum, similarly as the slicide strap interconnect.
Another local interconnection method is disclosed in U.S. Pat. No. 4,675,073, issued to me on June 23, 1987, and assigned to Texas Instruments Incorporated, incorporated herein by this reference. As disclosed therein, the desired local interconnect is formed by patterning the residual titanium compound, for example titanium nitride, from the direct reaction forming titanium silicide cladding of the diffusions and polysilicon gates. The titanium nitride is sufficiently conductive so that it is useful to make local interconnections between neighboring regions. The disclosed process uses carbon tetrafluoride (CF.sub.4) as the reactant in a plasma etch to remove the undesired titanium nitride faster than titanium silicide. This plasma etch using carbon tetrafluoride etches titanium nitride or titanium oxide at approximately twice the rate it removes titanium silicide. This technique also etches silicion oxides at twice the rate, and photoresist at five times the rate, as it etches titanium nitride or titanium oxide. Additionally, products of the etching process include solids that tend to adhere to the etching device. This requires extra maintenance and cleanup time that is nonproductive. Thus, a need has arisen for a method for producing a local interconnect with increased selectivity to the refractory metal compound of the local interconnect (e.g., titanium nitride or titanium oxide) relative to silicides, silicon oxides and photoresist, so that an additional layer of interconnection may be more consistently manufactured with precisely located interconnects and improved planarization compatible with sub-micron technology.
It is therefore an object of this invention to provide an etch for the residual material over insulating layers remaining from the direct react silicidation which has an increased etch rate ratio (i.e., improved selectivity) of the residual material relative to the silicide.
It is a further object of this invention to provide such an etch which also has improved etch selectivity (i.e., an increased etch rate ratio) of the interconnect relative to underlying insulating layers.
It is a further object of the present invention to provide such an etch with improved selectively to titanium nitride or titanium oxide with respect to titanium silicide, silicon dioxide and photoresist.
It is a further object of the present invention to provide such an etch which reduces the preventative maintenance and cleanup schedules and procedures by the use of a chlorine bearing agent as opposed to a flourine agent.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.